The trend in microelectronic circuitry is to implement new microprocessor logic circuitry which will have increase in performance speed, higher density and increased functions with minimal power input. Traditionally the integrated circuit designer must trade-off between speed and power dissipation with the result that the integrated circuit design favors meeting the speed requirements by fabrication of integrated circuits having multiple logic gates rated for functioning at the higher speed without being able to control the power consumption. The type of design employed by the designer to produce the foregoing type of design is known as a symmetrical design. FIGS. 1 and 2 depict the symmetrical design approach for manufacturing a MOS device having the source and drain regions doped symmetrically with concentrations of two dopant impurities D1 and D2. This approach to manufacturing MOS devices has limited applications and is considered adequate to channel lengths in the range of 0.25 .mu.m.
As the miniaturization of MOS devices continues and the channel lengths become less than 0.25 .mu.m, the need to customize devices also continues. As a solution, asymmetrical design approaches have been explored. The formation of individual asymmetric channel devices includes using an angled implant of an impurity on the source side of the channel of the device while masking the drain side so that a portion of the implant underlies the gate stack forming a more lightly doped region than the adjacent drain region. Exemplary is the above referenced pending application of one of the applicants of this invention, and the teachings of Odanaka et al., in a paper entitled "Potential Design and Transport Property of 0.1 .mu.m MOSFET with Asymmetrical Channel Profile", IEEE Transactions on Electron Devices, Vol. 44, No. 4 (April 1997). Both of these exemplary approaches fail to address the method of producing customized MOS devices with less than 0.25 .mu.m channel regions on multiple arrangement of MOS devices, such as in a logic gate. Pending application Ser. No. 08/909,044 teaches a particular approach for forming an asymmetrical MOS device on individual MOS devices by angularly implanting an impurity into the substrate at an angle ranging from 5 to 40 degrees. The Odanaka et al. paper teaches using Monte Carlo device simulation and process simulation to analyze device performance and transport property of 0.1 .mu.m n-MOSFET with asymmetric channel profile.
The benefit of utilizing the asymmetric channel on individual MOS devices is seen to exist for use on multiple arrangements of MOS devices, such as on logic gates. The main benefit in such applications is being able to control roll-off of threshold voltages even though an asymmetric channel device has a channel length in the 0.1 .mu.m range. Therefore, MOS devices can be densely packaged with the channel width Lg to be equal to the spacing Ls between MOS devices forming the logic gate, (ranging 50-200 nm), see generally FIG. 4. Additional benefits include being able to form MOS devices having extremely small junction capacitance, for example capacitances on the order of 50 fF (femtofarad), and a benefit of obtaining improved gate delays (20-50 pico-seconds for a 4-input Nand gate having a 50 fFload). Accordingly, a need is seen to exist for a method of optimizing the design of logic gate having multiple MOS devices by expanding upon the basic concept of producing asymmetric channel on single MOS devices. Thus, a primary object of the present invention is to provide a MOS semiconductor structure and process for producing logic gate integrated circuits having asymmetric channel design in each of the logic gate's MOS devices.